Table of contents
Any errata will be linked from the video itself on the front page and fixed in the slides, so there’s no need to keep checking back here.
Week 1 intro talk
Slide 7 referred to the “Tuesday live sessions” - Tuesday should have read Monday, these are the normal workshops you have timetabled from 1pm-3pm.
Week 5 video 4
Part of the video shows a version of slide 3 with 15 bits stored under “Contents” rather than 16 bits.
Week 7 video 3
Slide 4 makes the claim that in modern CPUs, usually CISC is better than RISC for high-speed high-power applications. In fact, the pendulum has been swinging back the other way in recent years and RISC is competitive with CISC in these domains as well.
Week 7 video 4
Slide 3 says we can set the clock speed to the propagation delay of the fastest stage; this should read the slowest stage.